1. Field of the Invention
The present invention generally relates to the control of instructions to a pipelined processor of a stored program dam processing machine and, more particularly, to an apparatus for controlling the instruction dispatch, issue, execution and memory update of a microprocessor capable of executing multiple instructions out-of-order every machine clock cycle.
2. Description of the Prior Art
A microprocessor that is capable of issuing and executing machine instructions out of order will in general permit loads to be executed ahead of stores. This feature permits a large performance advantage provided that the load address and the store address do not both have the same physical address. In typical programs, the frequency that a load proceeds ahead of the store and that their physical address matches is low. However, since the discovery of this store violation condition is typically late in the instruction execution pipeline, the recovery penalty can be quite severe. The recovery process typically involves invalidating the load instruction that caused the violation and all newer instructions in program order beyond the load instruction, and second reissuing the load instruction.
One approach to solve this problem in the prior art for a machine capable of executing instructions out of order was to permit only nonload/store instructions to execute out of order and restrict load and store instructions to execute in order. A second approach utilized in the prior art was to speculatively execute load/store instructions as well as nonload/store instructions and to perform collision recovery only when necessary. A third approach was to permit the load to execute only when it is determined safe to do so. The third approach requires that the virtual or real address of the store and load be computed to resolve that no store load collision exists which would require the store to issue and execute before the load in program order ahead of the store can issue and execute.